Additional copies of this document or other Intel literature maybe obtained from: Intel Corporation. Literature , and 80C51 Hardware. Description. The Intel AH is a MCS NMOS single-chip 8-bit microcontroller with 32 I/O lines, 2 Timers/Counters, Instruction Set Manual for the Intel AH. The MCS 51 CHMOS microcontroller products are fabricated on Intel’s reliable AN80C51 indicates an automotive temperature range version of the 80C51 in a.
Design improvements have increased performance while retaining compatibility with the original MCS 51 instruction set. Short, Standard, and Extended. Pins 40 and 20 are VCC and ground respectively. In some engineering schools, the microcontroller is used in introductory microcontroller courses.
The A register works in a similar fashion to the Iintel register of x86 processors. The requires an external oscillator circuit.
Set when banks at 0x08 or 0x18 are in use. PORT P2 pins 21 to CamelForth for the “. Views Read Edit View history. JNC offset jump if carry inhel. Retrieved 6 January MOV Cbit. ORL addressdata. As a conclusion, the architecture has not been altered, because the way in which the memory is connected to the processor follows the same principle defined in the basic architecture.
Set when addition produces a carry from bit 3 to bit 4. The A and B registers can store up to 8-bits of data each.
This section needs expansion. The MCS family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants.
One machine cycle has 6 states. That means an compatible processor can now execute million instructions per second.
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There are many commercial C compilers. This is “program store enable”. In other languages Add links.
The success of the Intel spawned a number of clones, which are collectively referred to as the MCS family of microcontrollers, which includes chips from vendors such as Atmel, Philips, Infineon, and Texas Instruments. XRL addressA.
PIN 40 and The high-order bit of the register bank. The 80C has fail-safe mechanisms, analog signal processing facilities and timer capabilities and 8 KB on-chip program memory. Some derivatives integrate a digital signal processor DSP.
The absolute memory address is formed by the high 5 bits of the PC and the 11 bits defined by the instruction. It features extended instructions  — see also the programmer’s guide  — and later variants with higher performance,  also available as intellectual property IP.
Enhancements mostly include new peripheral features and expanded arithmetic instructions. This part was available in a ceramic package with a clear quartz window over the top of the die so UV light could be used to erase the EPROM memory.
The last digit can indicate memory size, e. CS1 Russian-language sources ru CS1 Spanish-language sources es Webarchive template wayback links All articles with dead external links Articles with dead external links from October Articles containing potentially dated statements from All articles containing potentially dated statements Articles containing Russian-language text All articles with unsourced statements Articles with unsourced statements from May Articles containing potentially dated statements from Articles with unsourced statements from July Articles with unsourced statements from July Articles to be expanded from November All articles to be expanded Articles using small message boxes Articles to be expanded from May Commons category link is locally defined Wikipedia articles with BNF jntel Wikipedia articles with GND identifiers Wikipedia articles with LCCN identifiers.
JZ offset jump if zero. The original core ran at 12 clock 80×51 per machine cycle, with most instructions executing in one or two machine cycles. Views Read Edit View history. ANL Adata.
80C51 Microcontrollers | Tekmos Inc.
Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing. Register select 0, RS0. RLC A rotate left through carry.